MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 584

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Enhanced Mode Operation
Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue
condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized
simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW
and the pause flag is not set. The QADC64E sets the completion flag and the queue status becomes idle.
Examples of this situation are:
14.4.4
The QADC64E queuing mechanism allows the application to utilize different requirements for
automatically scanning input channels.
In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In
continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are
executed. The possible modes are:
14.4.4.1
When the disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution.
When both queue 1 and queue 2 are disabled, wait states are not encountered for IMB3 accesses of the
RAM. When both queues are disabled, it is safe to change the QCLK prescaler values.
14.4.4.2
Reserved mode allows for future mode definitions. When the reserved mode is selected, the queue is not
active. It functions the same as disabled mode.
14-42
•
•
•
•
•
The pause bit is set in CCW10 and EOQ is programmed into CCW10
During queue 1 operation, the pause bit set in CCW32, which is also BQ2
Disabled and reserved mode
Single-scan modes
— Software initiated single-scan mode
— External trigger single-scan mode
— External gated single-scan mode
— Periodic/Interval timer single-scan mode
Continuous-scan modes
— Software initiated continuous-scan mode
— External trigger continuous-scan mode
— External gated continuous-scan mode
— Periodic/Interval timer continuous-scan mode
Scan Modes
Disabled Mode
Reserved Mode
Do not use a reserved mode. Unspecified operations may result.
MPC561/MPC563 Reference Manual, Rev. 1.2
WARNING
Freescale Semiconductor