MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 928

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
When working in the masked mode, all internal breakpoints detected when MSR[RI] = 0 are lost.
Watchpoints detected in this case are not counted by the debug counters. Watchpoints detected are always
reported on the external pins, regardless of the value of MSR[RI].
Out of reset, the CPU is in masked mode. Programming the CPU to be in non-masked mode is done by
setting the BRKNOMSK bit in the LCTRL2 register. Refer to
Register
23.2.1.5
In order to facilitate the debugger utilities “continue” and “go from x”, the ignore first match option is
supported for instruction breakpoints. When an instruction breakpoint is first enabled (as a result of the
first write to the instruction support control register or as a result of the assertion of MSR[RI] when
operating in the masked mode), the first instruction will not cause an instruction breakpoint if the ignore
first match (IFM) bit in the instruction support control register (ICTRL) is set (used for “continue”).
When the IFM bit is clear, every matched instruction can cause an instruction breakpoint (used for “go
from x”). This bit is set by the software and cleared by the hardware after the first instruction breakpoint
match is ignored. Load/store breakpoints and all counter generated breakpoints (instruction and load/store)
are not affected by this mode.
23.2.1.6
Using the four compare types mentioned above (equal, not equal, greater than, less than) it is possible to
generate also two more compare types: greater than or equal and less than or equal.
This method does not work for the following boundary cases:
These boundary cases need no special support because they all mean ‘always true’ and can be programmed
using the ignore option of the load/store watchpoint programming (refer to
Breakpoints
23.2.2
There are four instruction address comparators A,B,C, and D. Each is 30 bits long, generating two output
signals: equal and less than. These signals are used to generate one of the following four events: equal, not
equal, greater than, less than.
23-14
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Generating the greater than or equal compare type can be done by using the greater than compare
type and programming the comparator to the needed value minus 1.
Generating the less than or equal compare type can be done by using the less than compare type
and programming the comparator to the needed value plus 1.
Less than or equal of the largest unsigned number (1111...1)
Greater than or equal of the smallest unsigned number (0000...0)
Less than or equal of the maximum positive number when in signed mode (0111...1)
Greater than or equal of the maximum negative number when in signed mode (1000...)
2.” The BRKNOMSK bit controls all internal breakpoints (I-breakpoints and L-breakpoints).
Instruction Support
Support”).
Ignore First Match
Generating Six Compare Types
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 23.6.10, “L-Bus Support Control
Section 23.2, “Watchpoints and
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