MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 774
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
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Quantity:
10 000
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Modular Input/Output Subsystem (MIOS14)
17.9.6.3
17-42
0:15
Bits
SRESET
Field
Addr
Name
AR
MDASM Data B (MDASMBR) Register
MSB
0
MDASMAR is the data register associated with channel A; its use varies with the different modes of
operation:
DIS mode: MDASMAR can be accessed to prepare a value for a subsequent mode selection.
IPWM mode: MDASMAR contains the captured value corresponding to the trailing edge of the measured
pulse.
IPM and IC modes: MDASMAR contains the captured value corresponding to the most recently detected
dedicated edge (rising or falling edge).
OCB and OCAB modes: MDASMAR is loaded with the value corresponding to the leading edge of the
pulse to be generated. Writing to MDASMAR in the OCB and OCAB modes also enables the
corresponding channel A comparator until the next successful comparison.
OPWM mode: MDASMAR is loaded with the value corresponding to the leading edge of the PWM pulse
to be generated.
NOTE: In IC, IPM, or IPWM mode, when a read to register A or B occurs at the same time as a counter
bus capture into that register and the counter bus is changing value, then the counter bus capture to that
register is delayed.
1
2
Figure 17-23. MDASM DataB Register (MDASMBR)
3
Table 17-19. MDASMAR Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
0x30 60DA, 0x30 60E2, 0x30 60EA, 0x30 60F2, 0x30 60FA
0x30 605A, 0x30 6062, 0x30 606A, 0x30 6072, 0x30 607A,
4
5
6
Undefined
7
Description
BR
8
9
10
11
12
Freescale Semiconductor
13
14
LSB
15
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