MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 393

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

9.5.13
When the MPC561/MPC563 is in slave mode, external master access to the MPC561/MPC563 internal
bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to
be executed. The RETRY signal functions as an output that signals the external master to release the bus
ownership and retry the access after one clock.
Figure 9-39
external access is retried and a pending internal-to-external access follows.
Freescale Semiconductor
CLKOUT
BR (input)
BG
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
Figure 9-38. Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)
TS (input)
Data
TA (output)
Contention Resolution on External Bus
describes the flow of an external master retried access.
MPC561/MPC563 Reference Manual, Rev. 1.2
O
O
Receive Bus Grant and Bus Busy Negated
Use the Internal Arbiter
O
O
Assert BB, Drive Address and Assert TS
Minimum 2 Wait States
Figure 9-40
Data is sampled
shows the timing when an
External Bus Interface
O
9-53