MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1123

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0x30 441C
0x30 441E
0x30 4420
0x30 4422
0x30 4424
0x30 4426
0x30 4428
0x30 442A
0x30 442C
0x30 442E
0x30 4500 –
0x30 450F
0x30 4510 –
0x30 451F
0x30 4520 –
0x30 452F
0x30 4530 –
0x30 453F
0x30 4540 –
0x30 454F
0x30 4550 –
0x30 455F
0x30 4560 –
0x30 456F
0x30 4570 –
0x30 457F
0x30 4580 –
0x30 458F
0x30 4590 –
0x30 459F
0x30 45A0 –
0x30 45AF
0x30 45B0 –
0x30 45BF
0x30 45C0 –
0x30 45CF
0x30 45D0 –
0x30 45DF
Address
Access
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B) (continued)
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
S
S
S
T
T
T
S
T
T
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
TPUMCR2_B
TPUMCR3_B
DCNR_B
CPR0_B
CPR1_B
SGLR_B
Symbol
CISR_B
ISDR_B
ISCR_B
LR_B
MPC561/MPC563 Reference Manual, Rev. 1.2
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—
—
—
—
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TPU3_B Channel Priority Register 0
TPU3_B Channel Priority Register 1
TPU3_B Channel Interrupt Status Register
TPU3_B Link Register
TPU3_B Service Grant Latch Register
TPU3_B Decoded Channel Number Register
TPU3_B Module Configuration Register 2
TPU3_B Module Configuration Register 3
TPU3_B Internal Scan Data Register
TPU3_B Internal Scan Control Register
TPU3_B Channel 0 Parameter Registers
TPU3_B Channel 1 Parameter Registers
TPU3_B Channel 2 Parameter Registers
TPU3_B Channel 3 Parameter Registers
TPU3_B Channel 4 Parameter Registers
TPU3_B Channel 5 Parameter Registers
TPU3_B Channel 6 Parameter Registers
TPU3_B Channel 7 Parameter Registers
TPU3_B Channel 8 Parameter Registers
TPU3_B Channel 9 Parameter Registers
TPU3_B Channel 10 Parameter Registers
TPU3_B Channel 11 Parameter Registers
TPU3_B Channel 11 Parameter Registers
TPU3_B Channel 11 Parameter Registers
Register
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
Size
16
16
16
16
16
16
16
Internal Memory Map
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Reset
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
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B-13