MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 622

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
15.3
The QSMCM memory maps, shown in
and dual SCI control and status registers, and the QSPI RAM. The QSMCM memory map can be divided
into supervisor-only data space and assignable data space. The address offsets shown are from the base
address of the QSMCM module. Refer to
memory map.
15-4
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
S
S
T
Memory Maps
1
0x30 500A
0x30 500C
0x30 500E
0x30 501A
0x30 501C
0x30 501E
0x30 5000
0x30 5002
0x30 5004
0x30 5006
0x30 5008
0x30 5010
0x30 5012
0x30 5014
0x30 5016
0x30 5018
Address
MSB
0
Dual SCI Interrupt Level (QDSCI_IL)
QSMCM Pin Assignment Register
See <XrefBlue>Table 15-10 for bit
QSPI Control Register 3 (SPCR3)
See <XrefBlue>Table 15-17 for bit
Reserved
See <XrefBlue>Table 15-5 for bit
2
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-1. QSMCM Register Map
Table 15-1
descriptions.
descriptions.
descriptions.
(PQSPAR)
Reserved
QSMCM Module Configuration Register (QSMCMMCR)
Figure 1-4
See <XrefBlue>Table 15-24 for bit descriptions.
See <XrefBlue>Table 15-25 for bit descriptions.
See <XrefBlue>Table 15-26 for bit descriptions.
See <XrefBlue>Table 15-27 for bit descriptions.
See <XrefBlue>Table 15-13 for bit descriptions.
See <XrefBlue>Table 15-15 for bit descriptions.
See <XrefBlue>Table 15-16 for bit descriptions.
See
See
SCI1Control Register 0 (SCC1R0)
SCI1Control Register 1 (SCC1R1)
and
QSPI Control Register 0 (SPCR0)
QSPI Control Register 1 (SPCR1)
QSPI Control Register 2 (SPCR2)
Section 15.5.1, “Port QS Data Register
QSMCM Test Register (QTEST)
SCI1 Status Register (SC1SR)
SCI1 Data Register (SC1DR)
for a diagram of the MPC561/MPC563 internal
Table 15-7
Table
QSMCM Port Q Data Register (PORTQS)
Reserved
Reserved
15-2, includes the global registers, the QSPI
for bit descriptions.
See <XrefBlue>Table 15-6 for bit descriptions.
QSMCM Data Direction Register (DDRQS)
Queued SPI Interrupt Level (QSPI_IL)
descriptions.
See <XrefBlue>Table 15-11 for bit
See <XrefBlue>Table 15-18 for bit
QSPI Status Register (SPSR)
descriptions.
descriptions.
Reserved
(PORTQS),” for bit
Freescale Semiconductor
LSB
15