MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 814
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Peripheral Pin Multiplexing (PPM) Module
The PPM Module has two data transmit signals, PPM_TX[0:1], and two data receive signals,
PPM_RX[0:1]. The amount of data transferred on these signals depends on the setting in
PPMPCR[OP_16_8]. If the PPM is configured to transfer data in 16 PPM_TCLK cycles per 16-bit word
then all data in TX_DATA[0:15] is transmitted on the PPM_TX0 signal, and all data is received into
RX_SHIFTER[0:15] from PPM_RX0. If the PPM is configured to transfer data in eight PPM_TCLK
cycles per 16-bit word then the eight bits will transfer on each of the data transfer signals.
In SPI mode the phase and polarity of PPM_TCLK is selectable by programming bits in the PPMPCR
register. PPM_TCLK can have normal polarity (active high) or inverted polarity (active low). There are
two clock phases available: valid data can be latched on the transition of PPM_TCLK from its active edge
to inactive edge, or valid data can be latched on the transition of PPM_TCLK from its inactive edge to
active edge.
See
settings.
18-8
PPM_TCLK(1)
PPM_TCLK(2)
Section 18.4.2, “PPM Control Register
PPM_TCLK(1) = SYSCLK/4
PPM_TCLK(2) = SYSCLK/2
Update(1)
Update(2)
Update(3)
Update(4)
Update(1) every PPM_TCLK(1)clock
Update(2) every PPM_TCLK(2) clock
Update(3) every second PPM_TCLK(2) clock
Update(4) every fourth PPM_TCLK(2) clock
SYSCLK
SYSCLK
Care must be taken when setting the sample rate with respect to the
OP_16_8 bit setting. For example if the PPM is transferring data on an
8-clock cycle, then setting the sample rate to every 16 clocks will result in
lost data.
Figure 18-7. Examples Of Several TCLK Frequencies and Sample Rates
MPC561/MPC563 Reference Manual, Rev. 1.2
(PPMPCR)” for more information on SPI mode PPM_TCLK
NOTE
Freescale Semiconductor
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