MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1094

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

MPC562/MPC564 Compression Features
When a change of flow occurs, the RCPU issues the new address in compression format. The address
extractor unit of the BBC extracts the base address to instruction memory. When the compressed memory
word is brought to the BBC from the memory, the ICDU uses the IP field of the RCPU-issued address to
decompress the instruction. The BBC provides compressed addresses of the decompressed and next
instructions to the RCPU together with the decompressed instruction.
Shortened word pointer fields of direct branches in compressed mode imply some limitations on compilers
that implement the PowerPC ISA architecture. They should generate binaries, with limited direct branch
displacements to make the compression possible.
If a conditional branch target, generated by a compiler, must be farther than the compression mode
limitation of 4 Kbytes, the compiler may generate a sequence of a conditional branch with opposite
condition to skip the following unconditional branch to the original target.
If the unconditional branch range is still not big enough, the compiler can use branch chains or indirect
branches.
A.2.5
The indirect branch destination address is copied without any change from one of the following RCPU
registers:
See the RCPU User’s Manual for more details.
These registers should contain (or be loaded by) the 32-bit compressed address of existing compressed
instructions to be used for correct branching.
The LR register is automatically updated by the correct value of the “next” instruction compressed address
during subroutine calls by using the ‘L’ - form of branch instructions (like bl or bcl).
The SRR0 register is updated by the correct return compressed address when exceptions are taken by the
RCPU, thus the rfi instruction obtains the correct return address from an exception handler.
A.2.6
Upon an exception, the RCPU core issues a regular 0xFFF00X00 or 0x00000X00 exception vector as
specified in the PowerPC ISA architecture. The compressed exception routines (or branches to them)
should start (reside) at the same location in memory as noncompressed ones. The BBC ICDU passes the
vectors unchanged to the MCU internal bus and provides corresponding compressed address to the RCPU
together with the first exception handler instruction opcode.
This scheme allows use of the BBC exception relocation feature regardless of the MCU operational mode.
The RESET routine vector is relocated differently in decompression on and in decompression off modes.
This feature may be used by a software code compression tool to guarantee that a vocabulary table
initialization routine is always executed before application code is running.
A-6
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LR
CTR
SRR0
Compressed Address Generation—Indirect Branches
Compressed Address Generation—Exceptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor