MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 769

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The polarity of the PWM output signal is selected by the EDPOL bit. The output flip-flop level can be
obtained at any time by reading the PIN bit.
If subsequent compares occur on channels A and B, the PWM pulses continue to be output, regardless of
the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-flop to the level
corresponding to a comparison on A or B respectively. Note that the FLAG line is not activated by the
FORCA and FORCB operations.
Figure 17-21
To generate PWM output pulses of different frequencies, the 16-bit comparator can have some of its bits
masked. This is controlled by bits MODE2, MODE1and MODE0. The frequency of the PWM output
(f
used as time reference and f
Freescale Semiconductor
PWM
16-bit Counter Bus
Output signal
Write 0x1000 to A
Write 0x1800 to B1
EDPOL = 0
) is given by the following equation (assuming the MDASM is connected to a 16-bit counter bus
Internal Register, not accessible to software
Register B1
Register B2
Register A
FLAG bit
provides an example of how the MDASM can be used for pulse width modulation.
If both channels are loaded with the same value, when a simultaneous match
on A and B occurs, the submodule behaves as if a simple match on B had
occurred except for the FLAG line which is activated. The output flip-flop
is reset and the value in register B1 is transferred to register B2 on the match.
Data registers A and B must be loaded with the values needed to produce
the desired PWM output pulse.
16-bit counter bus compare only occurs when the 16-bit counter bus is
updated.
A Compare
Figure 17-21. MDASM Output Pulse Width Modulation Example
0x1000
0x1800
0x1800
0x1000
SYS
is the frequency of the MIOS14 CLOCK):
MPC561/MPC563 Reference Manual, Rev. 1.2
Write to B1
0x1000
0x1500
0x1800
0x1100
B Compare
WARNING
NOTE
NOTE
0x1000
0x1800
0x1500
0x1500
Flag reset
by software
Write to B1
0x0000
0x1000
0x1700
0x1500
Modular Input/Output Subsystem (MIOS14)
A Compare
0x1000
0x1700
0x1700
0x1000
Flag reset
by software
B Compare
0x1000
0x1700
0x1700
0x1700
17-37