MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 251

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Each interrupt request from external lines and from USIU internal interrupt sources in the case of its
assertion will set a corresponding bit in SIPEND register. The individual SIPEND bits may be masked by
clearing an appropriate bit in SIMASK register.
6.1.4.4
The enhanced interrupt controller operation may be turned on by setting the EICEN control bit in the
SIUMCR register. In this mode the 32 IMB interrupt levels will be latched by USIU using eight IMB
interrupt lines and two lines of ilbs via the time multiplexing scheme defined by the UIMB module. In
addition to the IMB interrupt sources the external interrupts and timer interrupts are available in the same
way as in the regular scheme. In this mode, the UIMB module does not drive U-bus interrupt level lines.
Each interrupt request will set a corresponding bit in SIPEND2 or SIPEND3 registers. SIPEND2 an
SIPEND3 may be masked by clearing an appropriate bit in SIMASK2 or SIMASK3 registers.
The priority logic is provided in order to determine the highest unmasked interrupt request, and interrupt
code is generated in the SIVEC register. See
Freescale Semiconductor
1
This is the value in the 8 most significant bits of the SIVEC register (SIVEC[25:31]).
Number
10
11
12
13
14
15
8
9
Enhanced Interrupt Controller Operation
If the enhanced interrupt controller is enabled, a delay is required prior to
re-enabling interrupts. Before clearing an interrupt related register, clear the
MSR[EE] bit (EE = 0). Expect a vector offset of 0x0 if an interrupt is cleared
or disabled while MSR[EE] = 1. This vector should be handled as if no
interrupt has occured, that is, perform an rfi instruction. After clearing an
interrupt source, sufficient time must elapse before re-enabling the
MSR[EE] bit (EE = 1). This time should take longer than the time needed
for a load of the same register that was just cleared. To guarantee enough
time, include this load instruction before the instruction that sets MSR[EE].
Priority
Lowest
Level
Table 6-3. Priority of Interrupt Sources—Regular Operation
—
—
—
—
—
—
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MPC561/MPC563 Reference Manual, Rev. 1.2
Interrupt Source
Description
EXT_IRQ4
EXT_IRQ5
EXT_IRQ6
EXT_IRQ7
Level 4
Level 5
Level 6
Level 7
Table
NOTE
6-4.
Offset in Branch
Table (Hex)
0x0040
0x0048
0x0050
0x0058
0x0060
0x0068
0x0070
0x0078
System Configuration and Protection
SIVEC Interrupt Code
00100000
00100100
00101000
00101100
00110000
00110100
00111000
00111100
1
6-11