MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 437
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
MPC561MZP56R2
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Freescale Semiconductor
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Chapter 11
L-Bus to U-Bus Interface (L2U)
The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the
unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides
protection for data memory accesses.
The L2U is bidirectional. It allows load/store accesses not intended for the L-bus data RAM to go to the
U-bus. It also allows code execution from the L-bus data RAM and read/write accesses from the U-bus to
the L-bus.
The L2U directs bus traffic between the L-bus and the U-bus. When transactions start concurrently on both
buses, the L2U interface arbitrates to select which transaction is handled. The top priority is assigned to
U-bus to L-bus accesses; lower priority is assigned to the load/store accesses by the RCPU.
11.1
11.2
Freescale Semiconductor
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Non-pipelined master and slave on U-bus
— Does not start two back-to-back accesses on the U-bus
— Supports U-bus pipelining
— Retries back-to-back accesses from U-bus masters
Non-pipelined master and slave on the L-bus
Generates module selects for L-bus memory-mapped resources within a programmable,
contiguous block of storage
Programmable data memory protection unit (DMPU)
L-bus and U-bus snoop logic for the reservation protocol compatible with the PowerPC ISA
architecture
Show cycles for RCPU accesses to the CALRAM (none, all, writes)
— Protection for CALRAM accesses from the U-bus side (all accesses to the CALRAM from the
Supports four memory regions whose base address and size can be programmed
— Available sizes are 4 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes, 256
— Region must start on the specified region size boundary (modulo addressing)
— Overlap between regions is allowed
Each of the four regions supports the following attributes:
General Features
Data Memory Protection Unit Features
U-bus side are blocked once the CALRAM protection bit is set)
Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, and 16 Mybtes
MPC561/MPC563 Reference Manual, Rev. 1.2
11-1
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