MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 309

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Clocks and Power Control
The low-power divider block is controlled in the system clock control register (SCCR). The default state
of the low-power divider is to divide all clocks by one. Thus, for a 40-MHz system, the general system
clocks are each 40 MHz. Whenever power-on reset is asserted, the MF bits are set according to
Table
8-1,
and the division factor high frequency (DFNH) and division factor low frequency (DFNL) bits in SCCR
are set to the value of 0 (÷1 for DFNH and ÷2 for DFNL).
8.5
Internal Clock Signals
The internal clocks generated by the clocks module are shown in
Figure
8-4. The clocks module also
generates the CLKOUT and ENGCLK external clock signals. The PLL synchronizes these signals to each
other. The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR.
When the backup clock is functioning as the system clock, the backup clock is automatically selected as
the time base clock source and is twice the MPC561/MPC563 system clock.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-7