MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 817

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

18.4.1.1
The PPM module cannot, and should not, be put into stop mode while either the transmit or receive
operation is enabled in PPMPCR[ENTX] and/or PPMPCR[ENRX]. Furthermore, it should not be put into
stop mode if it is operating in continuous mode. In this case it should be switched to single transfer mode
first.
The following steps should be taken to ensure that stop mode is entered safely and without loss of data:
Freescale Semiconductor
1. If the PPM is operating in continous mode
2. If the PPM is enabled for transmit or receive
3. If the PPM is not enabled for transmit or receive
4. Set PPMMCR[STOP]
Bits
9:15
1:7
0
8
— switch to single transfer mode by clearing PPMPCR[CM]=0.
— set PPMPCR[STR] (TDM or SPI mode)
— Disable both PPMPCR[ENTX] and PPMPCR[ENRX]
— Wait until PPMPCR[STR] is cleared by the PPM module. This will be done when the next data
— Clear PPMPCR[STR] if necessary
When PPMMCR[STOP] is set, the PPM module enters stop mode and the PPM module clocks will
be stopped. While in stop mode, none of the PPM registers will be accessible, except for the
PPMPCR register.
If the STOP bit is clear, stop mode is disabled.
frame has been sent or received.
Entering Stop Mode
Name
STOP
SUPV
—
—
Stop Mode Enable. When the STOP bit is set and the PPM enters Stop Mode, the PPM module
clocks will be stopped. The PPM will only respond to accesses to the PPMMCR register. The
STOP bit can only be set when the PPM is disabled, (i.e., PPMPCR[ENTX] = 0 and
PPMPCR[ENRX] = 0). Writing to the STOP bit while either TX or RX is enabled will result in a
TEA (bus error access).
0 PPM clocks enabled
1 PPM clock disabled – PPM in Stop Mode.
Reserved
Supervisor/User Data Space. The SUPV bit places the PPM registers in either Supervisor or
User Data Space.
0 Access to PPMMCR, TX_CONFIG1/2, RX_CONFIG1/2 is restricted to supervisor-only.
1 All PPM registers are accessible in supervisor-only data space.
Reserved
Access to all other PPM registers is unrestricted.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 18-2. PPMMCR Bit Descriptions
Description
Peripheral Pin Multiplexing (PPM) Module
18-11