MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 624

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
15.4
The QSMCM global registers contain system parameters used by the QSPI and dual SCI submodules for
interfacing to the CPU and the intermodule bus. The global registers are listed in
15.4.1
When the STOP bit in QSMCMMCR is set, the IMB3 clock input to the QSMCM is disabled and the
module enters a low-power operating state. QSMCMMCR is the only register guaranteed to be readable
while STOP is asserted. The QSPI RAM is not readable in low-power stop mode. However, writes to RAM
or any register are guaranteed valid while STOP is asserted. STOP can be written by the CPU and is cleared
by reset.
System software must bring each submodule to an orderly stop before setting STOP to avoid data
corruption. The SCI receiver and transmitter should be disabled after transfers in progress are complete.
The QSPI can be halted by setting the HALT bit in SPCR3 and then setting STOP after the HALTA flag
is set in SPSR.
15.4.2
The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3 FREEZE signal
is asserted. FREEZE is asserted when the CPU enters background debug mode. Setting FRZ1 causes the
QSPI to halt on the first transfer boundary following FREEZE assertion. FREEZE causes the SCI1
transmit queue to halt on the first transfer boundary following FREEZE assertion.
15.4.3
The SUPV bit in the QMCR defines the assignable QSMCM registers as either supervisor-only data space
or unrestricted data space.
When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only space. For any access
from within user mode, the IMB3 address acknowledge (AACK) signal is asserted and a bus error is
generated.
15-6
1
2
Access
S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
S
S
S
T
QSMCM Global Registers
1
Low-Power Stop Operation
Freeze Operation
Access Protection
0x30 5000
0x30 5002
0x30 5004
0x30 5006
Address
MSB
0
See <XrefBlue>Table 15-5 for bit descriptions.
2
Dual SCI Interrupt Level (QDSCI_IL)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-2. QSMCM Global Registers
Reserved
QSMCM Module Configuration Register (QSMCMMCR)
See <XrefBlue>Table 15-4 for bit descriptions.
QSMCM Test Register (QTEST)
See <XrefBlue>Table 15-6 for bit descriptions.
Queued SPI Interrupt Level (QSPI_IL)
Reserved
Table
Freescale Semiconductor
15-2.
LSB
15