MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 604

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Enhanced Mode Operation
14.5.2
This section contains some conversion timing examples. Example 1 below shows the timing for basic
conversions where the following is assumed:
14-62
•
•
•
•
•
Q1 begins with CCW0 and ends with CCW3
CCW0 has pause bit set
CCW1 does not have pause bit set
External trigger rise-edge for Q1
CCW4 = BQ2 and Q2 is disabled
Q2:
Conversion Timing Schemes
T2
C1
(TRIGGER CAPTURED, RESPONSE DELAYED AFTER FREEZE)
C2
Q2:
Q1:
T2
C3
T1
C1
C1
C4
Q1:
T1
C2
C2
MPC561/MPC563 Reference Manual, Rev. 1.2
T2
Figure 14-41. CCW Freeze Situation 17
Figure 14-42. CCW Freeze Situation 18
Figure 14-43. CCW Freeze Situation 19
C1
PF2
C3
C2
(TRIGGERS IGNORED)
T2
FREEZE
FREEZE
FREEZE
C4
C3
Q2:
CF1
C1
C4
T2
CF1
C3
C2
C4
CF2
C4
C3
CF2
Freescale Semiconductor
C4
QADC S17
CF2
QADC S19
QADC S18