MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 645

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
The SPIFIE bit in SPCR2 enables the QSPI to generate an interrupt request upon assertion of the SPIF
status flag. Because it is buffered, the value written to SPIFIE applies only upon completion of the queue
(the transfer of the entry indicated by ENDPQ). Thus, if a single sequence of queue entries is to be
transferred (i.e., no WRAP), then SPIFIE should be set to the desired state before the first transfer.
If a sub-queue is to be used, the same CPU write that causes a branch to the sub-queue may enable or
disable the SPIF interrupt for the sub-queue. The primary queue retains its own selected interrupt mode,
either enabled or disabled.
The SPIF interrupt must be cleared by clearing SPIF. Subsequent interrupts may then be prevented by
clearing SPIFIE. Clearing SPIFIE does not immediately clear an interrupt already caused by SPIF.
15.6.4.3
QSPI Flow
The QSPI operates in either master or slave mode. Master mode is used when the MCU initiates data
transfers. Slave mode is used when an external device initiates transfers. Switching between these modes
is controlled by MSTR in SPCR0. Before entering either mode, appropriate QSMCM and QSPI registers
must be initialized properly.
In master mode, the QSPI executes a queue of commands defined by control bits in each command RAM
queue entry. Chip-select pins are activated, data is transmitted from the transmit RAM and received by the
receive RAM.
In slave mode, operation proceeds in response to SS pin assertion by an external SPI bus master. Operation
is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred
is controlled in a different manner. When the QSPI is selected, it automatically executes the next queue
transfer to exchange data with the external device correctly.
Although the QSPI inherently supports multi-master operation, no special arbitration mechanism is
provided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must
provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being set
nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be disabled by
clearing SPE in SPCR1.
Figure 15-18
shows QSPI initialization.
Figure 15-19
through
Figure 15-23
show QSPI master and slave
operation. The CPU must initialize the QSMCM global and pin registers and the QSPI control registers
before enabling the QSPI for either mode of operation. The command queue must be written before the
QSPI is enabled for master mode operation. Any data to be transmitted should be written into transmit
RAM before the QSPI is enabled. During wraparound operation, data for subsequent transmissions can be
written at any time.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
15-27