MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 214
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Burst Buffer Controller 2 Module
4.3.1
The exception vectors generated by the RCPU are 0x100 bytes apart from each other, starting at address
0x0000 0100 or 0xFFF0 0100, depending on the value of MSR[IP] bit in the RCPU.
If the exception table relocation is disabled by the ETRE bit in the BBCMCR register, the BBC transfers
the exception fetch address to the U-bus of the MPC561/MPC563 with no interference. In this case, normal
PowerPC ISA exception addressing is implemented.
If the exception table relocation is enabled, the BBC translates the exception vector into the exception
relocation address as shown in
(ba) must be placed. Each ba instruction branches to the required exception routine. These branch
instructions should be successive in that region of memory. That way, a table of branch instructions is
implemented. Executing the branch instruction causes the core to branch twice until it gets to the exception
routine.
Each exception relocation table entry occupies two words to support decompression on mode, where a
branch instruction can be more than 32 bits long. The branch table can be located in four locations in the
internal memory, the location is defined by BBCMCR[OERC] as shown in
4-8
1FFC
1F00
0
100
200
300
400
500
600
700
Exception Pointer by Core
ETR Operation
.
.
.
.
Figure 4-2. Exception Table Entries Mapping
Table
MPC561/MPC563 Reference Manual, Rev. 1.2
4-1. At that location, a branch instruction with absolute addressing
Decompression
Y
ON
N
1FFC
B8
10
8
0
Internal Memory Structure
Free Memory Space
branch to...
branch to...
branch to...
branch to...
branch to...
branch to ...
branch to...
branch to...
branch to...
branch to...
branch to...
branch to...
branch to...
branch to...
Table
.
.
.
.
4-2.
Freescale Semiconductor
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