MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 178
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
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Central Processing Unit
For a complete list of simplified mnemonics, see the RCPU Reference Manual. Programs written to be
portable across the various assemblers for the PowerPC ISA architecture should not assume the existence
of mnemonics not described in that manual.
3.10.3
The effective address (EA) is the 32-bit address computed by the processor when executing a memory
access or branch instruction or when fetching the next sequential instruction.
The PowerPC ISA architecture supports two simple memory addressing modes:
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the
effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address, the storage operand is considered to wrap around from the maximum effective
address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary
arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
3.11
The PowerPC ISA exception mechanism allows the processor to change to supervisor state as a result of
external signals, errors, or unusual conditions that arise in the execution of instructions. When exceptions
occur, information about the state of the processor is saved to certain registers, and the processor begins
execution at an address (exception vector) predetermined for each exception. Processing of exceptions
occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition
may be determined by examining a register associated with the exception — for example, the DAE/source
instruction service register (DSISR). Additionally, some exception conditions can be explicitly enabled or
disabled by software.
The PowerPC ISA architecture requires that exceptions be taken in program order; therefore, although a
particular implementation may recognize exception conditions out of order, they are handled strictly in
order with respect to the instruction stream. When an instruction-caused exception is recognized, any
unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered
the execute state, are required to complete before the exception is taken. For example, if a single
instruction encounters multiple exception conditions, those exceptions are taken and handled sequentially.
Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not
handled until all instructions currently in the execute stage successfully complete execution and report
their results.
3-34
•
•
EA = (rA|0) + 16-bit offset (including offset = 0) (register indirect with immediate index)
EA = (rA|0) + rB (register indirect with index)
Exception Model
Calculating Effective Addresses
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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