MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 130

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
HRESET. However, the signals must not cause any spurious conditions or consume an excessive amount
of power during reset. To prevent these conditions, the signals need to have a defined reset state.
Table 2-14
All signals are initialized to a “reset state” during reset. This state remains active until reset is negated or
until software disables the pull-up or pull-down device based on the signal functionality. Upon assertion
of the corresponding bits in the signal control registers and negation of reset, the signal acquires the
functionality that was programmed.
2.6.3
Power-on reset and hard reset affect the functionality of the signals out of reset. (During soft reset, the
functionality of the signals is unaltered.)
Upon assertion of the power-on reset signal (PORESET/TRST) the functionality of the signal is not yet
known to the RCPU. The weak pull-up or weak pull-down resistors are enabled. The reset configuration
word configures the system, and towards the end of reset the signal functionality is known. Based upon
the signal functionality, the pull-up or pull-down devices are either disabled immediately at the negation
of reset or remain enabled, as shown in
Because hard reset can occur when a bus cycle is pending, the PDMCR bits that enable and disable the
pull-up or pull-down resistors are set or reset synchronously to eliminate contention on the signals.
(PORESET/TRST affects these bits asynchronously.)
2.6.4
2.6.4.1
The pull resistors are enabled and disabled by the corresponding bits in the PDMCR register in the USIU
(see
1), the devices are disabled.
2.6.4.2
The 5-V/2.6-V multiplexed pad does not have a pull-up device. The pull-down will be controlled by the
corresponding bits in the PDMCR register. When this bit is negated, the pull-down is enabled, when
asserted the pull-down will be disabled.
2.6.4.3
For the signals that support debug, opcode tracking, and bus control functionality, the pull resistors will be
controlled by the SPRDS bit in the PDMCR register. During reset this signal will be synchronously used
2-32
Table
2-14). When those bits are negated (logic 0), the pull resistors are enabled. When asserted (logic
describes the reset state of the signals based on signal functionality.
Power-On Reset and Hard Reset
Pull-Up/Pull-Down
Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only
Signals
Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals
Special Pull Resistor Disable Control Functionality (SPRDS)
All pull-up/pull-down devices are disabled when all the signals are forced
to three state in JTAG mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
2-14.
NOTE
Freescale Semiconductor