MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 197

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.15.4.9
A decrementer exception occurs when no higher priority exception exists, the decrementer register has
completed decrementing, and MSR[EE] = 1. The decrementer exception request is canceled when the
exception is handled. The decrementer register counts down, causing an exception (unless masked) when
passing through zero. The decrementer implementation meets the following requirements:
The register settings for the decrementer exception are shown in
Freescale Semiconductor
1
•
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
Machine State Register (MSR)
Loading a GPR from the decrementer does not affect the decrementer.
Storing a GPR value to the decrementer replaces the value in the decrementer with the value in the
GPR.
Whenever bit 0 of the decrementer changes from zero to one, an exception request is signaled. If
multiple decrementer exception requests are received before the first can be reported, only one
exception is reported. The occurrence of a decrementer exception cancels the request.
If the decrementer is altered by software and if bit 0 is changed from zero to one, an interrupt
request is signaled.
Table 3-29. Register Settings following a Floating-Point Unavailable Exception (continued)
Decrementer Exception (0x0900)
Register
Register
Table 3-30. Register Settings Following a Decrementer Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
DCMPEN
[16:31]
Other
[0:15]
Other
Bits
Bits
ME
ME
LE
LE
All
IP
IP
No change
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
would have attempted to execute next if no exception
conditions were present.
Loaded from MSR[16:31]
No change
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
No change
Cleared to 0
Set to the effective address of the instruction that the processor
Cleared to 0
No change
Cleared to 0
Table
Setting Description
Setting Description
3-30.
Central Processing Unit
3-53