MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 104

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
2-6
IRQ4 / AT2 / SGPIOC4
IRQ5 / MODCK1 / SPGIOC5
IRQ[6:7] / MODCK[2:3]
CS[0:3]
WE[0:3] / BE[0:3] / AT[0:3]
Signal Name
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
1
1
2
4
4
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
O
O
O
O
I
I
I
I
I
IRQ4
MODCK1 until
reset negates,
then IRQ5
MODCK[2:3]
until reset
negates, then
IRQ[6:7]
CS[0:3]
Controlled by
RCW[ATWC].
See
Function after
Reset
Table
6-8.
1
Interrupt Request 4. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU.
Address Type 2. A bit from the address type bus which
indicates one of the 16 “address types” to which the address
applies. The address type signals are valid at the rising edge
of the clock in which the special transfer start (STS) is
asserted.
Port SGPIOC4. Allows the signal to be used as a
general-purpose input/output.
Interrupt Request 5. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU.
Mode Clock 1. Sampled at the negation of PORESET/TRST
in order to configure the phase-locked loop (PLL)/clock
mode of operation.
Port SGPIOC5. Allows the signal to be used as a
general-purpose input/output.
Interrupt Request [6:7]. One of the eight external signals
that can request, by means of the internal interrupt
controller, a service routine from the RCPU.
Mode Clock [2:3]. Sampled at the negation of
PORESET/TRST in order to configure the PLL/clock mode
of operation.
Chip Select [0:3]. These output signals enable peripheral or
memory devices at programmed addresses if defined
appropriately in the memory controller. CS0 or CS3 can be
configured to be the global chip select for the boot device.
Write Enable[0:3]/Byte Enable[0:3]. This output signal is
asserted when a write access to an external slave controlled
by the memory controller is initiated by the
MPC561/MPC563. It can be optionally asserted on all read
and write accesses. See WEBS bit definition in
WEn/BEn are asserted when data lanes shown below
contain valid data to be stored by the slave device.
– WE0/BE0 is asserted if the data lane DATA[0:7] contains
valid data to be stored by the slave device.
Address Type [0:3]. Indicates one of the 16 address types to
which the address applies. The address type signals are
valid at the rising edge of the clock in which the special
transfer start (STS) is asserted.
• WE1/BE1 is asserted if the data lane DATA[8:15]
• WE2/BE2 is asserted if the data lane DATA[16:23]
• WE3/BE3 is asserted if the data lane DATA[24:31]
contains valid data to be stored by the slave device.
contains valid data to be stored by the slave device.
contains valid data to be stored by the slave device.
Description
Freescale Semiconductor
Table
10-8.