MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1388

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

66-MHz Electrical Characteristics
G-82
M
A
B
C
D
E
G B_TPUCH12
H B_TPUCH8 B_TPUCH9
K B_TPUCH0 B_TPUCH1
N
F
J
L
B_T2CLK_P
CS4
B_TPUCH4 B_TPUCH5
JCOMP_RS
TI_B
TDI_DSDI_
MDI0
IRQ3_B_KR
_B_RETRY IWP0_VFL IWP1_VFL
VDDH
VDD
VSS
VSS
VSS
1
A_T2CLK_
PCS5
B_TPUCH1
3
TCK_DSCK
_MCKI
TMS_EVTI
_B
VSS
VDD
VSS
VSS
VSS
2
A_TPUCH
0
B_TPUCH
14
B_TPUCH
10
B_TPUCH
6
B_TPUCH
2
B_CNRX0 B_CNTX0
IRAMSTBY TDO_DSD
VSS
VSS
VDD
VSS
VSS
Figure G-66. MPC561/MPC563 Ball Map (Black and White, page 1)
3
B_TPUCH1
5
B_TPUCH1
1
B_TPUCH7
B_TPUCH3
O_MDO0
SGPIOC6_
FRZ_PTR_
QVDDL
VSS
VSS
VDD
VSS
VSS
4
A_TPUCH3 A_TPUCH7
A_TPUCH2 A_TPUCH6
A_TPUCH1 A_TPUCH4
VSS
5
MPC561/MPC563 Reference Manual, Rev. 1.2
A_TPUCH5
6
A_TPUCH
11
A_TPUCH
10
A_TPUCH
8
A_TPUCH
9
7
A_TPUCH15
A_TPUCH14
A_TPUCH12
A_TPUCH13
8
NVDDL
NVDDL
VSSA
VSSA
9
ALTREF
VDDA
VRL
VRH
10
A_AN3_A
NZ_PQB3
A_AN2_A
NY_PQB2
A_AN0_A
NW_PQB
0
A_AN1_A
NX_PQB1
VSS
VSS
VSS
VSS
VSS
VSS
11
A_AN51_P
QB7
A_AN50_P
QB6
A_AN48_P
QB4
A_AN49_P
QB5
VSS
VSS
VSS
VSS
VSS
VSS
12
A_AN55_
PQA3
A_AN54_
MA2_PQ
A2
A_AN52_
MA0_PQ
A0
A_AN53_
MA1_PQ
A1
VSS
VSS
VSS
VSS
VSS
VSS
13
A_AN56_P
QA4
A_AN58_P
QA6
A_AN59_P
QA7
A_AN57_P
QA5
VSS
VSS
VSS
VSS
VSS
VSS
14
VSS
VSS
VSS
VSS
VSS
VSS
Freescale Semiconductor
VSS
VSS
VSS
VSS
VSS
VSS