MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 212
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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Burst Buffer Controller 2 Module
When no match happens, the effective region is the global region.
The region attribute registers contain the region protection fields: PP, G, and CMPR. The protection fields
are compared to address attributes issued by the RCPU. If the access is permitted, the address is passed to
the BIU and further to the U-bus.
Whenever the IMPU detects access violation, the following actions are taken:
However, if the required address contains a show cycle attribute, the BIU delivers the access onto the
U-bus to obtain program tracking.
The exception vector (address) that the RCPU issues for this exception has a 0x1300 offset in the RCPU
exception vector table. The access violation status is provided in the RCPU SRR1 special purpose register.
The encoding of the status bits is as follows:
Only one bit is set at a time.
4.2.4
The BBC is operating as a U-bus slave when the IMPU registers, decompressor RAM (DECRAM) or
ICDU registers are accessed from the U-bus. The IMPU register programming is done using PowerPC ISA
mtspr/mfspr instructions. The ICDU configuration registers (DCCRs) and DECRAM are mapped into the
chip memory space and accessed by load/store instructions. DCCR and DECRAM accesses may be
disabled by BBCMCR[DCAE]. Refer to
(BBCMCR).”
4.2.5
Upon soft reset, the BBC switches to an idle state and all pending U-bus accesses are ignored, the ICDU
internal queue is flushed and the IMPU switches to a disabled state where all memory space is accessible
for both user and supervisor.
Hard reset sets some of the fields and bits in the BBC configuration registers to their default reset state.
Some bits in the BBCMCR register get their values from the reset configuration word.
All the registers are reset using HRESET; SRESET alone has no effect on them.
4-6
1. The request forwarded to the BIU is canceled
2. The RCPU is informed that the requested address caused an access violation by exception request.
•
•
•
•
SRR1 [1] = 0
SRR1 [3] = Guarded storage
SRR1 [4] = Protected storage or compression violation
SRR1 [10] = 0
Slave Operation
Reset Behavior
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 4.6.2.1, “BBC Module Configuration Register
Freescale Semiconductor
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