MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 910
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 910 of 1420
- Download datasheet (11Mb)
CALRAM Operation
22-14
Bits
3:19
20
21
0
1
2
Name
LCK
2CY
DIS
R0
D0
—
Write protection — This bit is designed to lock out writes to the CRAMMCR. While LCK = 0 the
register can be written repeatedly without restriction.
If LCK = 1, the register does not accept writes (i.e., the value of the register remains unchanged,
but the cycle terminates normally.)
In normal mode, this bit can only be set once and can only be cleared by reset.
0 writes to the CRAMMCR are unrestricted
1 writes to the CRAMMCR are ignored
In freeze mode, only the LCK bit may be written to zero if it was previously set.
Array disable — When set, this bit disables the CALRAM array.
In this mode, all reads and writes to the CALRAM array are ignored and a bus error is generated.
The CALRAM responds to register access while DIS = 1.
This is a low power mode for the module, since all internal functions will be disabled.
The module can be re-enabled by writing the DIS bit back to a zero. Reset will also re-enable the
module.
0 CALRAM module array access is enabled
1 CALRAM module array access is disabled
Two cycle mode — When set, this bit puts the CALRAM into a two cycle access mode operation
for CALRAM register accesses as well as array accesses.
This mode provides power savings by using the first cycle to decode any L-bus access for an
address match to where the array resides.
0 CALRAM module in one-cycle operation
1 CALRAM module in two-cycle operation
Reserved
Read-only/read-write privilege — If the data relocate (DR) bit is set in Machine Status Register
(MSR in RCPU) and R0 is also set, then write accesses are terminated with an error. If DR bit is
0, both reads and writes to the array block is allowed regardless of the value programmed in R0.
This bit controls the highest 8-Kbyte block (lowest address) of CALRAM in the associated array.
Likewise, R1, R2, and R3 control three other 8-Kbyte blocks in the same manner. See
for control bit address ranges.
R0 = 0 and DR = 0 readable and writable (array 8-Kbyte block)
R0 = 0 and DR = 1 readable and writable (array 8-Kbyte block)
R0 = 1and DR = 0 readable and writable (array 8-Kbyte block)
R0 = 1 and DR = 1 read only (array 8-Kbyte block)
Data-only/data-instruction privilege (Data type assignment) — If the data relocate (DR) bit is set
in Machine Status Register (MSR) and D0 is also set, then any access attempting to fetch an
instruction from the array block generates an error. If DR bit is 0, both data read and instruction
fetch from the array block is allowed, regardless of the value programmed in D0.
This bit controls the highest 8-Kbyte block (lowest address) of CALRAM in the associated array.
Likewise, D1, D2, and D3 control three other 8-Kbyte blocks in the same manner. See
for control bit address ranges.
D0 = 0 and DR = 0 data and/or Instruction (array 8-Kbyte block)
D0 = 0 and DR = 1 data and/or Instruction (array 8-Kbyte block)
D0 = 1 and DR = 0 data and/or Instruction (array 8-Kbyte block)
D0 = 1 and DR = 1 data only (array 8-Kbyte block)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 22-3. CRAMMCR Bit Descriptions
Description
Freescale Semiconductor
Table 22-4
Table 22-4
Related parts for MPC561MZP56
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
MPC5 1K0 5%
Manufacturer:
TE Connectivity
Datasheet:
Part Number:
Description:
MPC5 500R 5%
Manufacturer:
TE Connectivity
Datasheet:
Part Number:
Description:
MPC5 5K0 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
MPC5 5R0 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
MPC5 50K 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
MPC5 1R0 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
TOWER ELEVATOR BOARDS HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
TOWER SERIAL I/O HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
LCD MODULE FOR TWR SYSTEM
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
DAUGHTER LCD WVGA I.MX51
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
TOWER SYSTEM BOARD MPC5125
Manufacturer:
Freescale Semiconductor
Datasheet: