MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 944

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
23.4.5.1
The SGPIOC6/FRZ/PTR signal powers up as the PTR function and its function is controlled by the GPC
bits in the SIUMCR.
23.4.5.2
The power-up state of IWP[0:1]/VFLS[0:1] is controlled by setting the SIUMCR[DBGC]; see
They can also be set via the reset configuration word (See
(RCW)”). The FRZ state is indicated by the value 0b11 on the VFLS[0:1] signals.
23.4.5.3
The VFLS[0:1]/MPIO32B[3:4] signals power up as the MPIO32B[3:4] function and their function can be
changed via the VFLS bit in the MIOS14TPCR register. The FRZ state is indicated by the value 0b11 on
the VFLS[0:1] signals.
23.4.6
The development port consists logically of the three registers: development port instruction register
(DPIR), development port data register (DPDR), and trap enable control register (TECR). These registers
are physically implemented as two registers, development port shift register and trap enable control
register. The development port shift register acts as both the DPIR and DPDR depending on the operation
being performed. It is also used as a temporary holding register for data to be stored into the TECR. These
registers are discussed below in more detail.
23.4.6.1
The development port shift register is a 35-bit shift register. Instructions and data are shifted into it serially
from DSDI using DSCK (or CLKOUT depending on the debug port clock mode, refer to
“Development Port Serial Communications — Clock Mode
instructions or data are then transferred in parallel to the CPU, the trap enable control register (TECR).
When the processor enters debug mode it fetches instructions from the DPIR which causes an access to
the development port shift register. These instructions are serially loaded into the shift register from DSDI
using DSCK (or CLKOUT) as the shift clock. In a similar way, data is transferred to the CPU by moving
it into the shift register which the processor reads as the result of executing a “move from special purpose
register DPDR” instruction. Data is also parallel-loaded into the development port shift register from the
CPU by executing a “move to special purpose register DPDR” instruction. It is then shifted out serially to
DSDO using DSCK (or CLKOUT) as the shift clock.
23.4.6.2
The trap enable control register is a 9-bit register that is loaded from the development port shift register.
The contents of the control register are used to drive the six trap enable signals, the two breakpoint signals,
and the VSYNC signal to the CPU. The “transfer data to trap enable control register” commands will cause
the appropriate bits to be transferred to the control register.
23-30
Development Port Registers
SGPIO6/FRZ/PTR Signal
IWP[0:1]/VFLS[0:1] Signals
VFLS[0:1]/MPIO32B[3:4] Signals
Development Port Shift Register
Trap Enable Control Register
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 7.5.2, “Hard Reset Configuration Word
Selection”
)
as the shift clock. These
Freescale Semiconductor
Section 23.4.6.4,
Table
6-8.