MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 180

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
operating system should set the RI bit in the MSR at the end of each exception handler’s prologue (after
saving the program state) and clear the bit at the start of each exception handler’s epilogue (before
restoring the program state). Then, if an unordered exception occurs during the servicing of an exception
handler, the RI bit in SRR1 will contain the correct value.
3.11.4
In the RCPU, all synchronous (instruction-caused) exceptions are precise. When a precise exception
occurs, the processor backs the machine up to the instruction causing the exception. This ensures that the
machine is in its correct architecturally-defined state. The following conditions exist at the point a precise
exception occurs:
3.11.5
The setting of the exception prefix (IP) bit in the MSR determines how exceptions are vectored. If the bit
is cleared, the exception vector table begins at the physical address 0x0000 0000; if IP is set, the exception
vector table begins at the physical address 0xFFF0 0000.
the first instruction of the exception handler routine for each exception type.
3-36
1. Architecturally, no instruction following the faulting instruction in the code stream has begun
2. All instructions preceding the faulting instruction appear to have completed with respect to the
3. SRR0 addresses either the instruction causing the exception or the immediately following
4. Depending on the type of exception, the instruction causing the exception may not have begun
Vector Offset
execution.
executing processor.
instruction. Which instruction is addressed can be determined from the exception type and the
status bits.
execution, may have partially completed, or may have completed execution.
00000
00100
00200
00300
00400
00500
(hex)
Precise Exceptions
Exception Vector Table
In the MPC561/MPC563, the exception table can additionally be relocated
by the BBC module to internal memory and reduce the total size required by
the exception table (see
System reset, NMI interrupt
External Interrupt
Exception Type
Machine Check
Data Storage
Reserved
Reserved
Table 3-19. Exception Vector Offset Table
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 4.3, “Exception Table Relocation
NOTE
Section 3.15.4.1, “System Reset Exception and NMI
Section 3.15.4.2, “Machine Check Exception
Section 3.15.4.3, “Data Storage Exception
Section 3.15.4.5, “External Interrupt
Table 3-19
Instruction Storage
shows the exception vector offset of
Section
—
(ETR).”
1
Freescale Semiconductor
(0x0500)”
(0x0300)”
(0x0200)”
(0x0100)”