MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 704

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
16.3.3.1
The following considerations must be observed when programming bit timing functions.
16.3.4
The TouCAN has two error counters, the transmit (Tx) error counter and the receive (Rx) error counter.
Refer to
increasing and decreasing these counters are described in the CAN protocol, and are fully implemented in
the TouCAN. Each counter has the following features:
16-10
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If the programmed PRESDIV value results in a single system clock per one time quantum, then the
PSEG2 field in CANCTRL2 register must not be programmed to zero.
If the programmed PRESDIV value results in a single system clock per one time quantum, then the
information processing time (IPT) equals three time quanta; otherwise it equals two time quanta.
If PSEG2 equals two, then the TouCAN transmits one time quantum late relative to the scheduled
sync segment.
If the prescaler and bit timing control fields are programmed to values that result in fewer than 10
system clock periods per CAN bit time and the CAN bus loading is 100%, then any time the rising
edge of a start-of-frame (SOF) symbol transmitted by another node occurs during the third bit of
the intermission between messages, the TouCAN may not be able to prepare a message buffer for
transmission in time to begin its own transmission and arbitrate against the message which
transmitted the early SOF.
The TouCAN bit time must be programmed to be greater than or equal to nine system clocks, or
correct operation is not guaranteed.The duration of the synchronization segment, SYNC_SEG, is
not programmable and is fixed at one time quantum.
Eight-bit up/down-counter
Increment by eight (Rx error counter also increments by one)
Decrement by one
Avoid decrement when equal to zero
Rx error counter reset to a value between 119 and 127 inclusive, when the TouCAN transitions
from error passive to error active
Section 16.7, “Programming
System Clock
Table 16-8. Example System Clock, CAN Bit Rate, and S-Clock Frequencies (continued)
Frequency
Error Counters
(MHz)
Configuring the TouCAN Bit Timing
16
56
40
25
20
16
CAN Bit Rate
(MHz)
0.500
0.125
0.125
0.125
0.125
0.125
MPC561/MPC563 Reference Manual, Rev. 1.2
Model,” for more information on error counters. The rules for
Possible S-Clock
Frequency (MHz)
1, 1.25, 2.5
1, 2, 2.5
1, 2
1, 2
1, 2
1, 2
Possible Number of
Time Quanta/Bit
8, 16, 20
8,10, 20
8, 16
8, 16
8,16
2, 4
PRESDIV Value + 1
25, 20,10
20, 10, 8
Freescale Semiconductor
56, 28
40, 20
16, 8
16, 8