MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 953

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The assertion and negation of the freeze signal when in debug mode disable is controlled by the exception
cause register (ECR) and the debug enable register (DER) as described in
the freeze signal the software needs to program the relevant bits in the debug enable register (DER). In
order to negate the freeze line the software needs to read the exception cause register (ECR) in order to
clear it and perform an rfi instruction.
If the exception cause register (ECR) is not cleared before the rfi is performed the freeze signal is not
negated. Therefore it is possible to nest inside a software monitor debugger without affecting the value of
the freeze line although rfi may be performed a few times. Only before the last rfi the software needs to
clear the exception cause register (ECR).
The above mechanism enables the software to accurately control the assertion and the negation of the
freeze signal.
23.6
Table 23-14
sections,
“Development Port Data Register
the mtspr and mfspr instructions.
Freescale Semiconductor
Section 23.6.2, “Comparator A–D Value Registers
Development Support Registers
lists the registers used for development support in SPR number order, and the register
SPR Number
(Decimal)
144
145
146
147
148
149
150
151
152
153
Table 23-14. Development Support Programming Model
Comparator A Value Register (CMPA)
See
Comparator B Value Register (CMPB)
See
Comparator C Value Register (CMPC)
See
Comparator D Value Register (CMPD)
See
Exception Cause Register (ECR)
See
Debug Enable Register (DER)
See
Breakpoint Counter A Value and Control Register (COUNTA)
See
Breakpoint Counter B Value and Control Register (COUNTB)
See
Comparator E Value Register (CMPE)
See
Comparator F Value Register (CMPF)
See
MPC561/MPC563 Reference Manual, Rev. 1.2
(DPDR),” follow the same SPR order. The registers are accessed with
Table 23-17
Table 23-17
Table 23-17
Table 23-17
Table 23-18
Table 23-19
Table 23-20
Table 23-21
Table 23-22
Table 23-22
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Name
(CMPA–CMPD)” through
Figure
23-6. In order to assert
Section 23.6.13,
Development Support
23-39