MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 191
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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When a machine-check exception occurs, the processor does one of the following:
Which action is taken depends on the value of the MSR[ME] bit, whether or not debug mode was enabled
at reset, and (if debug mode is enabled) the values of the CHSTPE (checkstop enable) and MCIE (machine
check enable) bits in the debug enable register (DER).
processor is in the checkstop state, instruction processing is suspended and cannot be restarted without
resetting the core.
An indication is sent to the USIU which may generate an automatic reset in this condition. Refer to
Chapter 7,
The register settings for machine check exceptions are shown in
Freescale Semiconductor
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Takes a machine check exception;
Enters the checkstop state; or
Enters debug mode.
MSR[ME]
“Reset,” for more details.
Register Name
0
1
0
0
1
1
Debug Mode
Table 3-25. Register Settings following a Machine Check Exception
Enable
Table 3-24. Machine Check Exception Processor Actions
0
0
1
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
CHSTPE
16:31
10:15
X
X
X
X
0
1
5:9
Bits
2:4
All
0
1
2
2
2
Set to the effective address of the instruction that caused the
interrupt
MSR0
Set to 1 for instruction fetch-related errors and 0 for
load/store-related errors
Cleared to 0
MSR[5:9]
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
MCIE
X
X
X
X
0
1
Table 3-24
Action Performed when Exception Detected
Branch to machine-check exception handler
Branch to machine-check exception handler
Table
summarizes the possibilities. When the
Enter checkstop state
Enter checkstop state
Description
Enter debug mode
Enter debug mode
3-25.
Central Processing Unit
3-47
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