MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 211
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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The BIU may be programmed for burstable or non-burstable access. If the BIU is programmed for
burstable access, the U-bus address phase transaction is accompanied by the burst request attribute. If
burstable access is allowed by the U-bus slave, the BIU continues current access as burstable, otherwise
current access is executed as a single access. If any protection violation is detected by the IMPU, the
current U-bus access is aborted by the BIU and an exception is signaled to the RCPU.
Show cycle, program trace and debug port access attributes accompanying the RCPU access are forwarded
by the BIU along with the U-bus access.
4.2.1.2
See
mode.
4.2.2
The BBC may initiate and handle burst accesses on the U-bus. The BBCMCR[BE] bit determines whether
the BBC operates burst cycles or not. Burst requests are enabled when the BE bit is set. The BBC handles
non-wrap-around bursts with up to 4 data beats on the internal U-bus.
4.2.3
Instruction memory protection is assigned on a regional basis. Default operation of IMPU is done on a
global region. The IMPU has control registers which contain the following information: region protection
on/off, region base address, size and access permissions.
Protection logic is activated only if the RCPU MSR[IR] bit is set.
During each fetch request from the RCPU core to instruction memory, the address is compared to a value
in the region base address of enabled regions. Any address matching the specific region within its
appropriate size as defined in the region attribute register sets a match indication.
When more than one match indication occurs, the effective region is the region with the highest priority.
Priority is determined by region number. The lowest region number has the highest priority and the global
region has lowest priority.
Freescale Semiconductor
Appendix A, “MPC562/MPC564 Compression
Burst Operation of the BBC
Access Violation Detection
Decompression On Mode
The burst operation in the MPC561/MPC563 is useful if a user system
implements burstable memory devices on the external bus. Otherwise the
mode will cause performance degradation when running code from external
memory.
When the RCPU runs in serialized mode it is recommended that bursts be
disabled by the BBC to speed up MPC561/MPC563 operation.
Burst operation for decompression on and in debug mode is disabled
regardless of BBCMCR[BE] bit setting.
The BBC burst should be turned off if the USIU burst feature is enabled.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Features” for explanation of the decompression on
Burst Buffer Controller 2 Module
4-5
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