MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 373
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
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Quantity:
10 000
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9.5.7.1
The potential bus master asserts BR to request bus mastership. BR should be negated as soon as the bus is
granted, the bus is not busy, and the new master can drive the bus. If more requests are pending, the master
can keep asserting its bus request as long as needed. When configured for external central arbitration, the
MPC561/MPC563 drives this signal when it requires bus mastership. When the internal on-chip arbiter is
used, this signal is an input to the internal arbiter and should be driven by the external bus master.
9.5.7.2
The arbiter asserts BG to indicate that the bus is granted to the requesting device. This signal can be
negated following the negation of BR or kept asserted for the current master to park the bus.
When configured for external central arbitration, BG is an input signal to the MPC561/MPC563 from the
external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter
to the external bus master.
Freescale Semiconductor
1. Assert BR
1. Wait for BB to be negated.
Bus Request
Bus Grant
2. Assert BB to become next master
3. Negate BR
1. Perform data transfer
1. Negate BB
Acknowledge Bus Mastership
Release Bus Mastership
Operate as Bus Master
Requesting Device
Request the Bus
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 9-24. Bus Arbitration Flowchart
1. Negate BG (or keep asserted to park
1. Assert BG
Grant Bus arbitration
Terminate Arbitration
bus master
Arbiter
External Bus Interface
9-33
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