MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 546

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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QADC64E Enhanced Mode Operation
Accesses to supervisor-only data space is permitted only when the bus master is operating in supervisor
access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space addresses. See
Space.”
14.2.3
The QADC64E modules can be configured to operate in Legacy or Enhanced mode. Legacy mode is the
default state out of reset. The QADC64E modules are configured for Enhanced mode by a series of writes
14-4
1
0x30 4C14-
0x30 4E00-
0x30 4E80-
0x30 4F00-
0x30 4C0A EMUX
0x30 4C0C
0x30 4C0E
0x30 4DFF
0x30 4C00
0x30 4C02
0x30 4C04
0x30 4C06
0x30 4C08
0x30 4C10
0x30 4C12
0x30 4E7F
0x30 4EFF
0x30 4F7F
0x30 4FFF
0x30 4F80
Address
Registers are accessible only as supervisor data space
Legacy and Enhanced Modes of Operation
STOP FRZ
SIGN
CIE1
CIE2
CF1
MSB
0
TEST MODE
PF1
PIE
PIE
1
2
1
IRL1
SSE1
SSE2
CF2
0000 00
2
UNSIGNED LEFT JUSTIFIED
PF2 TOR
PORTQA
TR
DDRQA
MPC561/MPC563 Reference Manual, Rev. 1.2
G
3
Table 14-2. QADC64E_B Address Map
SIGNED LEFT JUSTIFIED
1
CWPQ1
4
TOR2
MQ1
MQ2
5
Reserved
LOC
K
P
6
Section 14.3.1.4, “Supervisor/Unrestricted Address
IRL2
FLI
RE
P
F
7
UNSIGNED RIGHT JUSTIFIED
QS
RESU
SUPV
IST
ME
8
9
QCLK PRESCALER
10
PORTQB
DDRQB
11
CHAN
BQ2
CWPQ2
00 0000
00 0000
12
CWP
13
Freescale Semiconductor
14
LSB
15
Reserved
Port Data
Control 0
Control 1
Control 2
Register
Direction
Interrupt
Config.
Status 0
Status 1
Module
Results
Results
Results
CCWs
Test
Port
1

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