MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 414
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Memory Controller
In
10-16
Figure
•
•
•
Because the TRLX bit is set, the assertion of the CS and WE strobes is delayed by one clock cycle.
Because ACS = 11, the assertion of CS is delayed an additional half clock cycle.
Because CSNT = 1, WE is negated one clock cycle earlier than normal. (Refer to
total cycle length is four clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— Two extra clock cycles are required due to the effect of TRLX on the assertion and negation of
Figure 10-12. Relaxed Timing — Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1)
10-13, note the following:
the CS and WE strobes.
Address
CLOCK
RD/WR
WE/BE
Data
OE
CS
TS
TA
MPC561/MPC563 Reference Manual, Rev. 1.2
ACS = 00
ACS = 10
Freescale Semiconductor
Figure
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