MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 947

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

23.4.6.5
When not in debug mode the development port starts communications by setting DSDO (the MSB of the
35-bit development port shift register) low to indicate that all activity related to the previous transmission
are complete and that a new transmission may begin. The start of a serial transmission from an external
development tool to the development port is signaled by a start bit. A mode bit in the transmission defines
the transmission as either a trap enable mode transmission or a debug mode transmission. If the mode bit
is set the transmission will only be 10 bits long and only seven data bits will be shifted into the shift
register. These seven bits will be latched into the TECR. A control bit determines whether the data is
latched into the trap enable and VSYNC bits of the TECR or into the breakpoints bits of the TECR.
23.4.6.6
The development port shift register is 35 bits wide but trap enable mode transmissions only use the
start/ready bit, a mode/status bit, a control/status bit, and the seven least significant data bits. The encoding
of data shifted into the development port shift register (through the DSDI pin) is shown in
Table 23-11
Freescale Semiconductor
CLKOUT
SRESET
First Start bit detected after DSDI negation (self clocked mode)
CLKEN
Internal clock enable signal asserts 8 clocks after SRESET
DSDI
negation if DSDI is negated. This enables clocked mode.
below:
Development Port Serial Communications — Trap Enable Mode
Serial Data into Development Port — Trap Enable Mode
DSDI negates following SRESET negation
to enable clocked mode.
0
1
Figure 23-11. Enabling Clock Mode Following Reset
2
MPC561/MPC563 Reference Manual, Rev. 1.2
3
4
5
6
7
8
9
10
11
12
13 14
15
Development Support
Table 23-10
23-33
and