MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 725
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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16.7.8
16.7.9
Freescale Semiconductor
SRESET
Bits
0:15
SRESET
SRESET
Field
Addr
Field MID
Field MID
Addr
Figure 16-16. Receive Global Mask Register: High (RXGMSKHI), Low (RXGMSKLO)
Free Running Timer (TIMER)
Receive Global Mask Registers (RXGMSKHI, RXGMSKLO)
MSB
0
TIMER
Name
MSB
28
14
16
1
1
0
1
0x30 7092 (RxGMSKLO_A); 0x30 7492 (RxGMSKLO_B); 0x30 7892 (RxGMSKLO_C)
0x30 7090 (RxGMSKHI_A); 0x30 7490 (RxGMSKHI_B); 0x30 7890 (RxGMSKHI_C);
MID
MID
27
13
17
1
1
1
The free running timer counter can be read and written by the CPU. The timer starts from
zero after reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the TouCAN bit-clock. During a message, it increments by one for
each bit that is received or transmitted. When there is no message on the bus, it increments
at the nominal bit rate.
The timer value is captured at the beginning of the identifier field of any frame on the CAN
bus. The captured value is written into the “time stamp” entry in a message buffer after a
successful reception or transmission of a message.
2
0x30 708A (TIMER_A); 0x30 748A (TIMER_B); 0x30 788A (TIMER_C)
Figure 16-15. Free Running Timer Register (TIMER)
MID
MID
26
12
18
1
1
2
3
MID
MID
MPC561/MPC563 Reference Manual, Rev. 1.2
25
11
19
1
1
3
Table 16-19. TIMER Bit Descriptions
4
MID
MID
24
10
20
1
1
4
5
MID
MID
23
21
1
9
1
5
0000_0000_0000_0000
6
MID
MID
22
22
6
1
8
1
7
MID
MID
TIMER
21
23
1
7
1
7
Description
8
MID
MID
20
24
8
1
6
1
9
MID
MID
19
25
1
5
1
9
10
MID
MID
18
10
26
1
4
1
MID
11
11
27
0
0
3
1
MID
12
28
12
1
1
2
1
CAN 2.0B Controller Module
MID
MID
17
13
29
1
1
1
13
MID
MID
16
14
30
1
0
1
14
MID
LSB
15
15
31
1
0
0
LSB
15
16-31
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