MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 52

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

18-26
18-27
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
20-1
20-2
20-3
20-4
20-5
20-6
20-7
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
lii
Figure
Number
Short Channels Register (SHORT_CH_REG) ..................................................................... 18-23
Scale Transmit Clock Register (SCALE_TCLK_REG)....................................................... 18-24
TPU3 Block Diagram ............................................................................................................. 19-1
TPU3 Interrupt Levels ............................................................................................................ 19-5
TCR1 Prescaler Control.......................................................................................................... 19-7
TCR2 Prescaler Control.......................................................................................................... 19-8
TPUMCR — TPU Module Configuration Register ............................................................. 19-11
DSCR — Development Support Control Register ............................................................... 19-12
DSSR — Development Support Status Register .................................................................. 19-14
TICR — TPU3 Interrupt Configuration Register ................................................................. 19-14
CIER — Channel Interrupt Enable Register......................................................................... 19-15
CFSR0 — Channel Function Select Register 0 .................................................................... 19-16
CFSR1 — Channel Function Select Register 1 .................................................................... 19-16
CFSR2 — Channel Function Select Register 2 .................................................................... 19-16
CFSR3 — Channel Function Select Register 3 .................................................................... 19-16
HSQR0 — Host Sequence Register 0................................................................................... 19-17
HSQR1 — Host Sequence Register 1................................................................................... 19-17
HSRR0 — Host Service Request Register 0 ........................................................................ 19-17
HSRR1 — Host Service Request Register 1 ........................................................................ 19-17
CPR0 — Channel Priority Register 0 ................................................................................... 19-18
CPR1 — Channel Priority Register 1 ................................................................................... 19-18
CISR — Channel Interrupt Status Register .......................................................................... 19-19
TPUMCR2 — TPU Module Configuration Register 2 ........................................................ 19-19
TPUMCR3 — TPU Module Configuration Register 3 ........................................................ 19-21
SIUTST — SIU Test Register .............................................................................................. 19-22
DPTRAM Configuration ........................................................................................................ 20-2
DPTRAM Memory Map......................................................................................................... 20-3
DPT Module Configuration Register (DPTMCR).................................................................. 20-3
RAM Array Base Address Register (RAMBAR)................................................................... 20-5
Multiple Input Signature Register High (MISRH) ................................................................. 20-5
Multiple Input Signature Register Low (MISRL) .................................................................. 20-6
MISC Counter (MISCNT) ...................................................................................................... 20-6
Block Diagram for a 512 Kbyte UC3F Module Configuration .............................................. 21-2
UC3F EEPROM Configuration Register (UC3FMCR) ......................................................... 21-5
UC3FMCRE— UC3F EEPROM Extended Configuration Register ..................................... 21-9
UC3F EEPROM High Voltage Control Register (UC3FCTL) ............................................ 21-11
PEGOOD Valid Time ........................................................................................................... 21-14
Shadow Information ............................................................................................................. 21-16
Hard Reset Configuration Word (UC3FCFIG) .................................................................... 21-16
512-Kbyte Array Configuration............................................................................................ 21-19
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
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