MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 210
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
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Burst Buffer Controller 2 Module
4.1.4
4.1.5
4.2
4.2.1
The BBC provides two instruction fetch modes: decompression off and decompression on. The operational
modes are defined by RCPU MSR[DCMPEN] bit. If the bit is set, the mode is decompression on.
Otherwise, it is in decompression off.
4.2.1.1
In this mode, the BBC bus interface unit (BIU) module transfers fetch accesses from the RCPU to the
U-bus. When a new access is issued by the RCPU, it is transferred in parallel to both the IMPU and the
BIU. The IMPU compares the address of the access to its region programming. The BIU checks if the
access can be immediately transferred to the U-bus, otherwise it requests the U-bus for the next clock.
4-4
•
•
•
•
•
•
•
•
•
•
•
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— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Two operation modes are available: decompression on and decompression off. Switch between
compressed and non-compressed user application software parts is possible.
Adaptive vocabularies scheme is supported; each user application can have its own optimum
vocabularies.
2 Kbytes RAM for decompression vocabulary tables
2 clock read/write accesses when used as a U-bus general-purpose RAM
4 clock load/store accesses from the L-bus
Byte, half-word (16-bit) or word (32-bit) read/write accesses and fetches
Special access protection functions
Low-power standby operation for data retention
Consists of eight “branch target entries” (BTE). Each entry contains:
— A 32-bit register that stores the target of historical change of flow (COF) address
— Four RAM entries, 38 bits each, which hold up to four valid instruction OPCODES (32 bits).
— A 32-bit register that stores the values used to calculate the address following the last valid
FIFO removal policy management is implemented for the eight BTEs
Software-controlled BTB enable/disable and invalidate
User transparent (that is, no user management is required)
Operation Modes
The six extra bits are used by ICDU in decompression on mode.
instruction.
DECRAM Key Features
Branch Target Buffer Key Features
Instruction Fetch
Decompression Off Mode
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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