MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 163

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.7.6
The link register (LR), SPR 8, supplies the branch target address for the branch conditional to link register
(bclrx) instruction, and can be used to hold the logical address of the instruction that follows a branch and
link instruction.
Note that although the two least-significant bits can accept any values written to them, they are ignored
when the LR is used as an address.
Both conditional and unconditional branch instructions include the option of placing the effective address
of the instruction after the branch instruction in the LR. This is done regardless of whether the branch is
taken.
3.7.7
The count register (CTR), SPR 9, is used to hold a loop count that can be decremented during execution
of branch instructions with an appropriately coded BO field. If the value in CTR is 0 before being
decremented, it is –1 afterward. The count register provides the branch target address for the branch
conditional to count register (bcctrx) instructio
Freescale Semiconductor
Reset
25:31
Reset
Bits
3:24
Field
Addr
Field
Addr
2
MSB
MSB
Link Register (LR)
Count Register (CTR)
0
0
BYTES
Name
CA
—
1
1
2
2
3
3
Carry (CA). In general, the carry bit is set to indicate that a carry out of bit 0 occurred during
execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract
from extended instructions set CA if there is a carry out of bit 0, and clear it otherwise. The CA
bit is not altered by compare instructions or other instructions that cannot carry, except that shift
right algebraic instructions set the CA bit to indicate whether any ‘1’ bits have been shifted out
of a negative quantity.
Reserved
This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx)
or Store String Word Indexed (stswx) instruction.
4
4 5 6 7 8
Table 3-10. Integer Exception Register Bit Descriptions
5
6
7
MPC561/MPC563 Reference Manual, Rev. 1.2
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Figure 3-10. Count Register (CTR)
9
Figure 3-9. Link Register (LR)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Branch Address
Unchanged
Loop Count
Unchanged
SPR 8
SPR 9
Description
Central Processing Unit
LSB
31
LSB
31
3-19