MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 779

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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17.10.1 MPWMSM Terminology
Terminology used in the MIOS14 pulse width modulation submodule includes the following:
Bits of resolution
Resolution
17.10.2 MPWMSM Features
Freescale Semiconductor
Counter
Clock
Output pulse width modulated (PWM) signal generation with no software intervention
Built-in 8-bit programmable prescaler clocked by the MCPSM
16-bit Down Counter
Next Period Register
8- bit Prescaler
MPWMCNTR
MPWMPERR
PS7 - PS0
(Ncount)
The MPWMSM contains a 16-bit modulus down-counter that counts from the
desired loaded value to 0x0001. The term “bits of resolution” is used in this
document to indicate the size of the equivalent free running binary counter. To
cover the worst case, the number of bits is rounded to the lower number. For
example, if the counter is preset with a value between 128 and 255, it is said to
have seven bits of resolution. If it is preset with a value between 256 and 511, it is
said to have eight bits of resolution, and so on.
The term “resolution” is used in this document to define the minimum MPWMSM
output increment in time units.
= 0x0001
FLAG
Request Bus
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 17-25. MPWMSM Block Diagram
LOAD
FREN
EN
Pulse Width Register
Next Pulse Width
<= Comparator
MPWMPULR1
MPWMPULR2
Register
16-bit
TRSP
Submodule bus
Flip-Flop
Output
EN
Modular Input/Output Subsystem (MIOS14)
Output
POL
Buffer
PIN
Output
Logic
DDR
Output
Signal
Output
Logic
17-47

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