MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 722

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
16.7.5
16-28
SRESET
CNRX0
Signal
Bits
8:15
2:3
4:5
6:7
0
1
Field
Addr
Control Register 1 (CANCTRL1)
1
2
CANCTRL1
MSB
BOFFMSK
TXMODE[1:0]
RXMODE
ERRMSK
TXMODE
Full CMOS drive indicates that both dominant and recessive levels are driven by the chip.
Open drain drive indicates that only a dominant level is driven by the chip. During a recessive
level, the CNTX0 signal is disabled (three stated), and the electrical level is achieved by external
pull-up/pull-down devices. The assertion of both Tx mode bits causes the polarity inversion to be
cancelled (open drain mode forces the polarity to be positive).
0
RX1
Name
X
X
—
1X
00
01
1
0x30 7086 (CANCTRL1_A); 0x30 7486 (CANCTRL1_B); 0x30 7886 (CANCTRL1_C)
RX0
0
1
2
Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
Reserved
Receive signal configuration control. These bits control the configuration of the CNRX0
signals. Refer to
Transmit signal configuration control. This bit field controls the configuration of the CNTX0
signals. Refer to
See
CANCTRL0
Full CMOS
Full CMOS
Open drain
3
0 CNRX0 signal is interpreted as a dominant bit
1 CNRX0 signal is interpreted as a recessive bit
0 CNRX0 signal is interpreted as a recessive bit
1 CNRX0 signal is interpreted as a dominant bit
Table 16-16
Figure 16-12. Control Register 1 (CANCTRL1)
Table 16-15. Transmit Signal Configuration
Table 16-14. Rx MODE[1:0] Configuration
Table 16-13. CANCTRL0 Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
4
1
1
2
5
; positive polarity (CNTX0 = 0 is a dominant level)
; negative polarity (CNTX0 = 1 is a dominant level)
; positive polarity
Table
Table
and
6
Section 16.7.5, “Control Register 1
16-14.
16-15.
0000_0000_0000_0000
TransmitSignal Configuration
7
SAMP
Receive Signal Configuration
8
Description
—
9
TSYNC LBUF
10
(CANCTRL1).”
11
—
12
Freescale Semiconductor
13
PROPSEG
14
LSB
15