MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 376
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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External Bus Interface
Figure 9-27
9-36
1
2
External master will be granted external bus ownership if EARP is greater than the internal access priority.
Parked access is instruction or data access from the RCPU which is initiated on the internal bus without
requesting it first in order to improve performance.
Instruction access
External access
Parked access
illustrates the internal finite-state machine that implements the arbiter protocol.
Data access
Table 9-4. Priority Between Internal and External Masters over External Bus
Type
No Longer
Needs the Bus
MPC500 Device
BR = 1
External Device With Higher
Priority than the Current Internal
Bus Master Requests the Bus
BG = 1
BB = three
state
2
IDLE
External Master
Requests Bus
BR = 0
Figure 9-27. Internal Bus Arbitration State Machine
MPC561/MPC563 Reference Manual, Rev. 1.2
external → external/internal
Internal → external
Internal → external
Internal → external
Direction
MCU Needs
the Bus
External Master
Release Bus
Device Owner
MPC500
External
BG = 0
BB = three
state
BG = 1
BB = 0
Owner
Internal Master With Higher
Priority than the External Device
Requires the Bus
EARP (could be programmed to 0 – 7)
MPC500 Device
MPC500 Device
Still Needs
the Bus
BB = 1
Bus
MPC500
BG = 1
BB = three
state
Device
Priority
Wait
0
3
4
BB = 0
Freescale Semiconductor
1
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