MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 30

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

23.4.4
23.4.5
23.4.5.1
23.4.5.2
23.4.5.3
23.4.6
23.4.6.1
23.4.6.2
23.4.6.3
23.4.6.4
23.4.6.5
23.4.6.6
23.4.6.7
23.4.6.8
23.4.6.9
23.4.6.10
23.4.6.11
23.5
23.5.1
23.6
23.6.1
23.6.2
23.6.3
23.6.4
23.6.5
23.6.6
23.6.7
23.6.8
23.6.9
23.6.10
23.6.11
23.6.12
23.6.13
24.1
24.1.1
24.2
24.2.1
Freescale Semiconductor
Paragraph
Number
Software Monitor Debugger Support ......................................................................... 23-38
Development Support Registers ................................................................................. 23-39
Features Summary ........................................................................................................ 24-1
Modes of Operation ...................................................................................................... 24-3
Development Serial Data Out ................................................................................. 23-29
Freeze Signal ........................................................................................................... 23-29
Development Port Registers ................................................................................... 23-30
Freeze Indication ..................................................................................................... 23-38
Register Protection .................................................................................................. 23-40
Comparator A–D Value Registers (CMPA–CMPD) .............................................. 23-41
Exception Cause Register (ECR) ............................................................................ 23-41
Debug Enable Register (DER) ................................................................................ 23-43
Breakpoint Counter A Value and Control Register ................................................ 23-45
Breakpoint Counter B Value and Control Register ................................................ 23-46
Comparator E–F Value Registers (CMPE–CMPF) ................................................ 23-46
Comparator G–H Value Registers (CMPG–CMPH) .............................................. 23-47
L-Bus Support Control Register 1 .......................................................................... 23-47
L-Bus Support Control Register 2 .......................................................................... 23-48
I-Bus Support Control Register (ICTRL) ............................................................... 23-51
Breakpoint Address Register (BAR) ...................................................................... 23-53
Development Port Data Register (DPDR) .............................................................. 23-53
Functional Block Diagram ........................................................................................ 24-2
Reset Configuration .................................................................................................. 24-3
SGPIO6/FRZ/PTR Signal ................................................................................... 23-30
IWP[0:1]/VFLS[0:1] Signals .............................................................................. 23-30
VFLS[0:1]/MPIO32B[3:4] Signals ................................................................... 23-30
Development Port Shift Register ........................................................................ 23-30
Trap Enable Control Register ............................................................................. 23-30
Development Port Registers Decode .................................................................. 23-31
Development Port Serial Communications — Clock Mode Selection ............... 23-31
Development Port Serial Communications — Trap Enable Mode .................... 23-33
Serial Data into Development Port — Trap Enable Mode ................................. 23-33
Serial Data Out of Development Port — Trap Enable Mode ............................. 23-34
Development Port Serial Communications — Debug Mode ............................. 23-35
Serial Data Into Development Port ..................................................................... 23-35
Serial Data Out of Development Port ................................................................. 23-36
Fast Download Procedure ................................................................................... 23-37
MPC561/MPC563 Reference Manual, Rev. 1.2
READI Module
Contents
Chapter 24
Title
Number
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