MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 223
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Section 4.6.2.3, “Region Attribute Registers
Attribute Register
4.6
4.6.1
The BBC consists of three separately addressable sections within the internal chip address space:
4.6.1.1
Freescale Semiconductor
1. BBC and IMPU control registers. These are mapped in the SPR registers area and may be
2. Decompressor vocabulary RAM (DECRAM). The DECRAM array occupies the 2-Kbyte physical
3. Decompressor class configuration registers (DCCR) block. It consists of 15 decompression class
SPR Number
(Decimal)
programmed by using the RCPU mtspr/mfspr instructions.
memory (8 Kbytes of the MPC561/MPC563 address space is allocated for DECRAM).
configuration registers. These registers are available for word wide read/write accesses through
U-bus. The registers occupy a 64-byte physical block (8-Kbyte chip address space is allocated for
the register block).
528
529
560
BBC Programming Model
Address Map
BBC Special Purpose Registers (SPRs)
(MI_GRA)” for details.
Access (Hex)
Address for
External
0x2100
0x2300
0x2110
Master
0x2F 8000
0x2F 87FF
0x2F 8800
0x2F 9FFF
0x2F A000
0x2F A03F
Figure 4-6. MPC561/MPC563 Memory Map
IMPU Global Region Attribute Register (MI_GRA). See
descriptions.
External Interrupt Relocation Table Base Address Register (EIBADR). See
Table 4-9
BBC Module Configuration Register (BBCMCR). See
MPC561/MPC563 Reference Manual, Rev. 1.2
for bits descriptions.
Table 4-3. BBC SPRs
(MI_RA[0:3]),” and
Reserved
DCCR0 – DCCR15
DECRAM
2 Kbytes
Register Name
Section 4.6.2.4, “Global Region
Table 4-4
Table 4-8
Burst Buffer Controller 2 Module
for bits descriptions
for bits
4-17
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