MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 775

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

17.9.6.4
The MDASMSCRD and the MDASMSCR are the same registers accessed at two different addresses.
Reading or writing to one of these two addresses has exactly the same effect.
The duplication of the SCR register allows coherent 32-bit accesses when using an RCPU.
17.9.6.5
The status and control register gathers a read only bit reflecting the status of the MDASM signal as well
as read/write bits related to its control and configuration.
The signal input status bit reflects the status of the corresponding signal when in input mode. When in
output mode, the PIN bit only reflects the status of the output flip-flop.
Freescale Semiconductor
Bits
0:15
Nam
BR
e
MDASM Status/Control Register (MDASMSCRD) (Duplicated)
MDASM Status/Control Register (MDASMSCR)
MDASMBR is the data register associated with channel B; its use varies with the different modes of
operation.
Writing to register B always writes to B1 and, depending on the mode selected, sometimes to B2. Reading
register B either reads B1 or B2 depending on the mode selected.
In the DIS mode, MDASMBR can be accessed to prepare a value for a subsequent mode selection. In this
mode, register B1 is accessed in order to prepare a value for the OPWM mode. Unused register B2 is hidden
and cannot be read, but is written with the same value when register B1 is written.
In the IPWM mode, MDASMBR contains the captured value corresponding to the leading edge of the
measured pulse. In this mode, register B2 is accessed; buffer register B1 is hidden and is not readable.
In the IPM and IC modes, MDASMBR contains the captured value corresponding to the previously dedicated
edge (rising or falling edge). In this mode, register B2 is accessed; buffer register B1 is hidden and is not
readable.
In the OCB and OCAB modes, MDASMBR is loaded with the value corresponding to the trailing edge of the
pulse to be generated. Writing to MDASMBR in the OCB and OCAB modes also enables the corresponding
channel B comparator until the next successful comparison. In this mode, register B2 is accessed; buffer
register B1 is hidden and is not readable.
In the OPWM mode, MDASMBR is loaded with the value corresponding to the trailing edge of the PWM pulse
to be generated. In this mode, register B1 is accessed; buffer register B2 is hidden and cannot be accessed.
NOTE: In IC, IPM, or IPWM mode, when a read to register A or B occurs at the same time as a counter bus
capture into that register and the counter bus is changing value, then the counter bus capture to that register
is delayed.
The user should not write directly to the address of the MDASMSCRD. This
register’s address may be reserved for future use and should not be accessed
by the software to ensure future software compatibility.
Table 17-20. MDASMBR Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
WARNING
Description
Modular Input/Output Subsystem (MIOS14)
17-43