MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 837

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

19.3.9
Timer count register 2 (TCR2), like TCR1, is clocked from the output of a prescaler. The T2CG (TCR2
clock/gate control) bit and the T2CSL (TCR2 counter clock edge) bit in TPUMCR determine T2CR2 pin
functions. Refer to
The function of the T2CG bit is shown in
When T2CG is set, the external T2CLK pin functions as a gate of the DIV8 clock (the TPU3 system clock
divided by eight). In this case, when the external TCR2 pin is low, the DIV8 clock is blocked, preventing
it from incrementing TCR2. When the external TCR2 pin is high, TCR2 is incremented at the frequency
of the DIV8 clock. When T2CG is cleared, an external clock from the TCR2 pin, which has been
synchronized and fed through a digital filter, increments TCR2. The duration between active edges on the
T2CLK clock pin must be at least nine system clocks.
TPUMCR3[TCR2PSCK2] and TPUMCR[TCR2] determine how the clock source is divided to provide
the output, see
Freescale Semiconductor
EPSCKE
System
Clock
DIV2
Prescaler Control for TCR2
Table
Table
19-5.
Enhanced
19-4.
Prescaler
2,4,6,...64
Prescaler
Figure 19-4
T2CSL
4, 32
0
0
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-4. TCR2 Counter Clock Source
Figure 19-3. TCR1 Prescaler Control
illustrates the TCR2 pre-divider and pre-scaler control.
Figure
PSCK
Mux
T2CG
0
1
0
1
19-4.
Rise and fall transition T2CLK
Rise transition T2CLK
Fall transition T2CLK
Gated system clock
Prescaler
1,2,4,8
TCR1
TCR2 Clock
TCR1
Time Processor Unit 3
19-7