MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 905

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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If the CLPS bit in OVLCR register is set, then each of the eight region sizes is forced to be 4 bytes long as
shown in
contiguous address space in CALRAM, for example, from 0x3F FFE0 to 0x3F FFFF. The remainder (4
Kbytes – 32 bytes) is not only available for normal array access but also contiguous with a 28-Kbyte
non-overlay array.
Freescale Semiconductor
Figure
22-7, regardless of the value programmed in the RGN_SIZE field. These 32 bytes occupy
0x3F 8000
0x3F F000
0x3F FFFF
Figure 22-6. CALRAM Address Map (CLPS = 0)
MPC561/MPC563 Reference Manual, Rev. 1.2
4-Kbyte Overlay Area
Non-Overlay Area)
CALRAM
(28-Kbyte
CALRAM
32-Kbyte
CALRAM
CALRAM Operation
22-9

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