MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1179
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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0
ADDRESS OFFSETS
1
0x30XXWA
0x30XXWC
0x30XXWE
0x30XXW0
0x30XXW2
0x30XXW4
0x30XXW6
0x30XXW8
Figure D-15. MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode
2
0
0
0
3
1
1
1
0
0
cChannel Function Select
cHost Sequence
cHost Service Request
cChannel Priority
cChannel Interrupt Enable 0 – Channel Interrupt Disabled
cChannel Interrupt Status
= Written By RCPU
= Written By TPU
NAME
0
1
MPC561/MPC563 Reference Manual, Rev. 1.2
2
3
xxxx – MCPWM Function Number.
Assigned during microcode assembly.
See
00 – Edge-Aligned Mode
01 – Slave A Type Center-Aligned Mode
10 – Slave B Type Center-Aligned Mode
11 – Slave C Type Center-Aligned Mode
00 – No Host Service (Reset Condition)
01 – Initialize As Slave (Inverted)
10 – Initialize As Slave (Normal)
11 – Initialize As Master
00 – Disabled
01 – Low Priority
10 – Medium Priority
11 – High Priority
1 – Channel Interrupt Enabled
0 – Channel Interrupt Not Asserted
1 – Channel Interrupt Asserted
4
PARAMETER RAM
CONTROL BITS
Table D-1
= Written by RCPU and TPU
= Unused Parameters
5
CURRENT_HIGH_TIME
B_FALL_TIME_PTR
B_RISE_TIME_PTR
TEMP_STORAGE
6
HIGH_TIME
7
OPTIONS
BITS
8
9
10 11 12 13 14 15
W = Channel Number
For address offsets: XX=41 for
TPU_A, 45 for TPU_B
YY=40 for TPU_A,
See
PRAM Address Offset Map.
44 for TPU_B
Table 19-24
0x30YY1C – 0x30YY1E
0x30YY0C – 0x30YY12
0x30YY18 – 0x30YY1A
0x30YY14 – 0x30YY16
ADDRESSES
0x30YY0A
0x30YY20
TPU3 ROM Functions
for the
Param 0
Param 1
Param 2
Param 3
Param 4
Param 5
Param 6
Param 7
D-27
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