MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 485

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

all of the status register fields contain read-only data. The four flag bits and the two trigger overrun bits
are cleared by writing a zero to the bit after the bit was previously read as a one.
Freescale Semiconductor
SRESET
Field CF1
Addr
Bits
0
MSB
0
Name
CF1
PF1
1
CF2
Queue 1 Completion Flag. CF1 indicates that a queue 1 scan has been completed. The
scan completion flag is set by the QADC64E when the input channel sample requested by
the last CCW in queue 1 is converted, and the result is stored in the result table.
The end-of-queue 1 is identified when execution is complete on the CCW in the location
prior to that pointed to by BQ2, when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF1 is set and interrupts are enabled for that queue completion flag, the QADC64E
asserts an interrupt request at the level specified by IRL1 in the interrupt register
(QADCINT). The software reads the completion flag during an interrupt service routine to
identify the interrupt request. The interrupt request is cleared when the software writes a
zero to the completion flag bit, when the bit was previously read as a one. Once set, only
software or reset can clear CF1.
CF1 is maintained by the QADC64E regardless of whether the corresponding interrupt is
enabled. The software polls for CF1 bit to see if it is set. This allows the software to
recognize that the QADC64E is finished with a queue 1 scan. The software acknowledges
that it has detected the completion flag being set by writing a zero to the completion flag
after the bit was read as a one.
2
PF2 TOR1 TOR2
3
Figure 13-12. Status Register 0 (QASR0)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-14. QASR0 Bit Descriptions
0x30 4810 (QASR0_A); 0x30 4C10 (QASR0_B)
4
5
0000_0000_0000_0000
6
7
Description
QS
8
9
10
11
QADC64E Legacy Mode Operation
12
CWP
13
14
LSB
15
13-21