MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 930

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
23.2.2.1
There are two load/store address comparators E, and F. Each compares the 32 address bits and the cycle’s
attributes (read/write). The two least-significant bits are masked (ignored) whenever a word is accessed
and the least-significant bit is masked whenever a half-word is accessed. (For more information refer to
Section 23.2.1.2, “Byte and Half-Word Working
equal and less than. These signals are used to generate one of the following four events (one from each
comparator): equal, not equal, greater than, less than.
There are two load/store data comparators (comparators G,H) each is 32 bits wide and can be programmed
to treat numbers either as signed values or as unsigned values. Each data comparator operates as four
independent byte comparators. Each byte comparator has a mask bit and generates two output signals:
equal and less than, if the mask bit is not set. Therefore, each 32 bit comparator has eight output signals.
These signals are used to generate the “equal and less than” signals according to the compare size
programmed (byte, half-word, word). When operating in byte mode all signals are significant, when
operating in half-word mode only four signals from each 32 bit comparator are significant. When operating
in word mode only two signals from each 32 bit comparator are significant.
From the new “equal and less than” signals and according to the compare type programmed one of the
following four match events are generated: equal, not equal, greater than, less than. Therefore, from the
two 32-bit comparators eight match indications are generated: Gmatch[0:3], Hmatch[0:3].
According to the lower bits of the address and the size of the cycle, only match indications that were
detected on bytes that have valid information are validated, the rest are negated. Note that if the cycle
executed has a smaller size than the compare size (e.g., a byte access when the compare size is word or
half-word) no match indication will be asserted.
Using the match indication signals four load/store data events are generated in the following way.
The four load/store data events together with the match events of the load/store address comparators and
the instruction watchpoints are used to generate the load/store watchpoints and breakpoint according to the
programming.
23-16
1
Event Name
‘&’ denotes a logical AND, ‘|’ denotes a logical OR
(G | H)
(G&H)
G
H
Load/Store Support
(Gmatch0 | Gmatch1 | Gmatch2 | Gmatch3)
(Hmatch0 | Hmatch1 | Hmatch2 | Hmatch3)
((Gmatch0 & Hmatch0) | (Gmatch1 & Hmatch1) | (Gmatch2 & Hmatch2) | (Gmatch3 & Hmatch3))
((Gmatch0 | Hmatch0) | (Gmatch1 | Hmatch1) | (Gmatch2 | Hmatch2) | (Gmatch3 | Hmatch3))
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 23-7. Load/Store Data Events
Modes”). Each comparator generates two output signals:
Event Function
1
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