MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 514

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
The MCU IMB3 clock frequency is the basis of the QADC64E timing. The QADC64E requires that the
IMB3 clock frequency be at least twice the QCLK frequency. The QCLK frequency is established by the
combination of the PSH and PSL parameters in QACR0. The 5-bit PSH field selects the number of IMB3
clock cycles in the high phase of the QCLK wave. The 3-bit PSL field selects the number of IMB3 clock
cycles in the low phase of the QCLK wave.
Example 1 in
IMB3 clock and with PSL = 7 the QCLK remains low for 8 IMB3 clock cycles. Example 2 shows that
when PSH = 11, QCLK is high for 12 IMB3 clock cycles and with PSL = 7, QCLK is low for 8 IMB3
clock cycles. Finally, example 3 shows that with PSH = 7 and PSL = 7, QCLK alternates between high and
low every 8 IMB3 cycles.
13-50
QCLK EXAMPLES
Example
Number
IMB3 CLOCK
1
2
3
56 MHz EX1
40 MHz EX2
32 MHz EX3
Table 13-21
PSA is maintained for software compatibility but has no functional benefit
to this version of the module.
F
SYS
Frequency
56 MHz
40 MHz
32 MHz
Control Register 0 Information
Figure 13-25. QADC64E Clock Programmability Examples
shows that when the PSH = 19, the QCLK remains high for 20 cycles if the
Table 13-21. QADC64E Clock Programmability
MPC561/MPC563 Reference Manual, Rev. 1.2
PSH
19
11
7
PSA
NOTE
0
0
0
30 CYCLES
PSL
7
7
7
Input Sample Time (IST) =0b00
QCLK
(MHz)
2.0
2.0
2.0
QADC64E QCLK EX
Freescale Semiconductor
Conversion Time
(µs)
7.0
7.0
7.0